EDA News eI Monday January 19, 2004 From: EDACafe ÿÿ Previous Issues _____ http://www.mentor.com/fpga _____ About This Issue eI ATE and/or Embedded Test A tantalizing look at some of the issues involved _____ January 12 - 16, 2004 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ If you're an aficionado of Test, autumn is your special season. The International Test Conference - ITC - is a distinctly fall event, attended each year by legions of loyal members of the Test Fraternity. This year ITC will be held in Charlotte, NC, from October 26th to the 28th and, as always, I'm sure a good time will be had by all. Consider the following conversation then, to be a January hors d'ourve in advance of the year's main course being served up way off in October. It's a roundtable discussion between four guys in Test, guys who know a lot about the subject and who were willing to answer a set of questions about the current integration, or lack thereof, between ATE [automated test equipment] technologies and DFT [design-for-test] technologies. The conversation took place in a conference call on Monday, January 12th, and the participants included: 1 - Stephen Pateras, Senior Director, Corporate Product Marketing, at LogicVision Inc. - received his Ph.D. in EE from McGill University. 2 - Ric Dokken, Co-Founder and Vice President of Software Development at Inovys Corp. - has a BSEET from DeVry College. 3 - David Hsu, Director of Marketing for Test and Formal Verification at Synopsys, Inc. - has an MBA from Santa Clara University, an MSCS from Stanford, and a BSCS from MIT. 4 - Sergio Perez, Vice President for Sales at Advantest America Inc. and Founder/Current Vice Chairman of the Semiconductor Test Consortium - has a BSE from Harvey Mudd College and an MBA from Harvard. Meanwhile, before you start in on the roundtable, it might be useful to hear how the companies that each of these gentlemen work for position themselves. Per the company: "LogicVision provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip." Per the company: "Inovys Corp. supplies advanced test solutions for semiconductor companies who require economical structural ATE systems and EDA-to-Test software. Inovys has pioneered the low-cost desktop tester which combines seamless ATPG [Automatic Test Pattern Generation]-ATE-EDA integration with advanced failure analysis tools utilizing DFT methodology." Per the company: "Synopsys, Inc. creates leading EDA tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers." Per the company: "Advantest is a world leader in the test and measurement industry, supplying cutting-edge products and services vital to the growth of the electronics, telecommunications, and semiconductor industries. Advantest's businesses can be classified into one of four categories: optical measuring instruments, semiconductor test systems, handler & device interfaces, and nanotechnology." The ATE/Embedded Test Roundtable Q: Where are you all sitting at this moment and how did you get interested in test? Stephen: I'm sitting in San Jose. I got my Ph.D. in the area of test. Ric: I'm sitting in Pleasanton, California. Way back in 1986, I started at LTX as a college grad. David: I'm sitting in Sunnyvale, California. I started in test by supporting VLSI technology and the "vector hospital" back in 1986. Sergio: I'm sitting in Chandler, near Phoenix, Arizona. It's been so long for me [laughing], I don't remember how I got involved in test. Q: Geographically, where are your customers located? Stephen: LogicVision's customers are all over the U.S., and in Japan, Taiwan, and Europe. Ric: The Inovys customer base is global. David: That's an interesting question. We measure market penetration by our Design Compiler installed base. At this point, Synopsys is probably at one test license for every two synthesis licenses out there. Sergio: The Advantest customer base is global in nature. Q: Can we reduce the costs associated with "Big Iron" ATE, or do we really even want to? What about "Little Iron" - workstations or PCs being used as less expensive post-production test equipment? Also, who coined the phrase, "embedded test." Stephen: You've already seen that [cost reduction]. Everyone from the Big Iron companies to all of these DFT companies are certainly coming out with lower-cost ATE. But, the largest portion of the costs of test is not in the equipment. They're in the handlers, the probe cards, the engineering. While you can reduce the cost of ATE, it's the human resource costs that [constitute the majority of the expense in test]. Ric: What you're seeing today is that some IDMs [integrated device manufacturers] have integrated their own low-cost test vehicles and are using that equipment for the sole purpose of reducing test costs. David: It's not easy for me to say. Originally, 3 years ago or more, when we started working with the ATE vendors, they thought we wanted to take away some of their revenue. But they can now see, that that has not been the reality. In terms of whether customers are using Big Iron or Little Iron, those decisions are being made based on objectives other than just cost. Sergio: It's a lot more complex than just reducing the cost of ATE. We reduce costs with each generation [of ATE equipment that we produce], in synch with Moore's Law. However, ATE capital expenditure [for a company] only represents 25 percent of the total cost of test. Everything that we do at Advantest, we do to reduce that cost. But ATE is just one of many tools that are used in test. Stephen: We see embedded test - and by the way, LogicVision coined the phrase, "embedded test" - and DFT, in general, as not just a way of reducing the cost of test, but as a way of keeping up with the test requirements. You can't test 50 million transistors on a chip, or 50 million gates, with just an ATE approach. You need to have something on-chip, as well. We're now seeing that belief accepted by a larger portion of the industry [than was previously true] - particularly in the area of memory BIST [built-in self test]. Sergio: There's agreement that at 250 million transistors [on-chip], you can't test without having embedded structures on the chip. I agree 100 percent that we need the help of embedded test [for these complex devices]. David: I'll agree with that, but the question remains - is there a commercial market for embedded test. Up 'til now, customers have needed this [capability], but as vendors, we need to enable this [process], so that buying licenses for [tools that insert test structures on-chip] is feasible. The business issues here aid the technology issues. Ric: I would echo what's been said here - the point that the transistor count today is such that [the chip] can't be tested just by using a functional testing methodology. At the same time, the [design] mechanisms that employ embedded test are, by nature, lowering the cost of the tester equipment. Q: How wide spread do you think the acceptance is for embedded test? Is the reduced cost of on-chip real estate having an effect? Stephen: Everyone has a different pain level, working at different design complexities, so the adoption rate for embedded test varies for every company. The fact that the testing of embedded memories is always done using embedded test [means that for memory vendors, embedded test is a reality]. Embedded test for embedded logic or some hybrid [of scan and BIST] using tools from Synopsys or Mentor, means that maybe we've got 50-precent acceptance for logic designers. [Meanwhile, going forward], you're going to see more embedded test for mixed-signal structures. David: I remember seeing a paper from the 1970's discussing the first use of scan chains. Adoption for that type of test structure has been there for 30 years. But in terms of an overall adoption [of embedded test], that happened when designers had the tools that allowed those structures to be inserted. But [earlier], if the structure was too big or too [costly in terms of real estate] it didn't happen. I'd say the tools probably weren't there until the mid-90's. Sergio: Customers have always needed to get to market with a high level of quality in their products. I think the best way [to think of it] is to say that we've been using embedded test structures since the 1970's and 80's, but we were talking about 1,000 transistors or gates back then - and half of the chip would have to be used for the test structure. [Today], the complexity of the chip has increased the need for testability, but the number of transistors available for the test structures has also increased. Ric: I wish I could remember the quote - it was from about a dozen years ago - but I think it was Intel that said that they weren't buying into this notion of putting additional DFT structures on a chip, because if you looked at what it cost for that 10-percent more die space needed for test structures versus the costs of ATE, it just wasn't worth it. But in recent years, with the submicron and nanometer processes, people are now saying, "gates are free." And the emerging tools from the EDA environment allows the burden to come off of the designer and onto the tools for employing those DFT structures. Now it's not about increasing the cost of real estate, it's about not increasing the cost [of lower yields]. Q: Are there significant power issues associated with all of this? Stephen: It's a matter of scheduling power [to the device under test]. You can always provide for more power to the device [to drive the test structures] from your test equipment, but we've always complained that there wasn't enough power [designed into the products] to drive the DFT structures on-chip [from the ATE]. David: I disagree. The scheduling issue really just presents more problems for the designers. You can always add more power to a tester, but I would say that once our customers have the tools, they're saying there are much more structured ways of getting power to the test structures. Stephen: People are designing hierarchically these days. With BIST, you can self test each core. [The concept] is inherent in how you add BIST to a design. There may be 150 different BIST controllers on a chip that come with full control. In reality, it's the test engineer then that has [to solve] the power problem. David: I reassert my small objections. One attribute is that there are myriad dimensions to the problems of physical partitioning. For instance, in a graphics processors there will be partitions that have nothing to do with test partitioning. In hierarchical design, you need to rely on other power strategies [than just scheduling]. Sergio: In terms of power, we see it at two levels. We're always planning for the providing of power to the devices - sometimes it's a huge amount of power. Some of our customers are tell us that they want 500 or 600 mAmps of power into their systems, but we see the physical need to limit power to the devices. Just look at your laptop. It has to have the fan working all the time. [Heat on the device is an issue.] From the ATE vendor's perspective, we're definitely designing systems to support high levels of power on the chip, but we've got to have a way to power the device and to cool the device at the same time [during testing]. Ric: The ATE side of the power issue is a management [issue]. Sergio just explained that there are complexities in how the device gets cooled. You need heat sinks, etc. But for the EDA test companies, the bigger issue is the one being addressed by Stephen and David. It's not whether the ATE is delivering [adequate] power; it's whether the package that the device goes into can handle [that level] of power. A higher rate of transistor switching is required and you need to do your scheduling [correctly] if you want to handle the power consumption correctly. David: What best illustrates this is the power consumption. You've seen a bunch of stuff from Synopsys lately describing power. You have to sprinkle power considerations into these test tools. And, you need power constraints and validation after the fact for inserting signal integrity constraints. Stephen: There's no doubt that there are complexities in dealing with power, and that there are different ways of dealing with it - scheduling, partitioning, lower scan rates, dealing with the different clocking of scan versus functional testing. There are a number of techniques available. On the EDA test side, [these techniques can be handled] in the automation of the tools. Ric: As I see it, on the other side of the device - after the design has been sent into an engineering or test environment. I often ask the question of our customers, 'How much power should the tester be providing?' In fact, however, our customers are very much in the dark about their projections, about what their demands for power will be. David and Stephen are talking about techniques that are deployable that they can take to market [in their tools]. But to the general population, [designers and test engineers], it continues to be a very confusing issue. David: Power is one of the fundamental strategic design issues - that's part of what Ric is talking about. Customers have a terrible time in planning for [on-chip test structures]. If you run the part of the device [which includes the test structures], it pulls power and heats up the device big time. We're working on a concerted program that works across all of these problems and will be having announcements soon in this area. Stephen: Power is always an issue, and it's becoming an even larger issue with [test structures on-chip]. The LogicVision tools are allowing customers to deal with the power consumption of a device under test, and not just the average power, but the peak power as well. There are IR drops, etc., that have to be monitored and we've got techniques to handle those issues. Q: What kind of impact are IEEE standards having in this area? Stephen: As far as test is concerned, I'm not really aware of any work with regards to power. But certainly, IEEE standards have been hugely important in test - the P1500 standard for core reuse, for example, and the 1450.6 standard [Core Test Language working group for the STIL standard] are proving very useful. Ric: Just as Stephen said, the IEEE 1450 STIL [Standard Test Interface Language], the P1500 [core test architecture], and the 1149 JTAG [Joint Test Action Group boundary scan] standards have all been useful. However, none of the IEEE standards have done anything in the area of power. David: I think that IEEE standards are often good only after the fact - [slow adoption until customers could get EDA tools, but few EDA tools until there was demand for increased adoption]. On the hardware/software side, the adoption of the 1149.1 JTAG standard is a chicken-and-egg situation. And in the P1500, there's nothing new there. Synopsys has been promoting highly these types of initial steps - the core test language part of P1500, now called P1450.6, which is part of the IEEE 1450 STIL standard - for over 3 years as a means of describing cores. Now IEEE has moved off to the STIL standard. Although, [it's true that] standards do provide some means for describing the expectation of core power use. Sergio: In terms of the IEEE - back in the early 90's, we went through a program that was doing STIL, but it never came out as an issue. I don't know of any group in IEEE that has focused on power. I don't really see what IEEE can do [in the are of power]. In the case of testing, we've made design changes in our tools to address the unpredictable and dynamic nature of high power. We're even working on it in the Semiconductor Test Consortium. Q: How do the partnerships work between EDA vendors who provide DFT insertion tools and the ATE vendors today? Stephen: We have our LV [LogicVision] Ready Partner Program with the ATE vendors who have been integrating our back-end software into their testers for several years now. Today every piece of ATE equipment is "LV Ready" and that's important. BIST is only as good as the integration is - and when our customers have effective access to tools for DFT structures on their devices, the ATE vendors win. Our technologies are strongly complementary. We work with all the ATE vendors because our customers are using pretty much everyone out there. Having said that, we don't need those partnerships to allow our customers to use our tools. A number of our customers have switched ATE vendors due to this, because we could work with all partners to make them LV ready - not to force additional costs. Ric: I would make a couple of points here. One - although the LV interface is a proprietary interface, there's been more effort within the IEEE standards, so that it's not proprietary to each ATE/DFT hook-up. There are important amounts of communication that need to go in both directions. Two - whether we're talking about Stephen's tools [from LogicVision] or David's tools [from Synopsys], we not just sending tools out into a battleship-type situation. We want to have results both ways. Partnering between EDA vendors and ATE vendors is required to make things easier for the customers. LogicVision pretty much pioneered the efforts where the software of each is talking to the other. In terms of EDA companies, however, there's definitely more effort in the STIL standard in one direction - and that's information going back from the ATE to the EDA provider. David: There are two dimensions to this, following up on Ric's comments. It's absolutely the case that partnering it not the end, but a means to the end. The end point is better failure evaluation and increased revenue to the customers. It's a backwards loop - Synopsys believe in STIL, and we were [pushing for standards there] back in 1997, before it was something [that anyone wanted to pursue]. Today, we work with all of the EDA vendors in an open way - in behavior, format, STIL - we work collaboratively. I'll note that our friends at Advantest had a very nice demo at Semico in Japan recently. Our TetraMAX provided the utility in that flow. Synopsys doesn't try to derive revenue from the vendors for that. As far as who we choose to work with - our baseline is that our format and STIL is open. We make our TetraMAX products visible - [openness] that the customers will always drive. It's true that we'll put in place a larger effort when we're driven by [requests from] large customers, but there is no desire on the part of Synopsys whatsoever to make our tools proprietary or de-facto standards. Putting thing in a proprietary or encrypted format would be kind of dumb. Certainly, that's true in the case of the backward thinking of the tester. Sergio: Who do we work with? That's really determined by the customers. We're trying to help the customers be successful, and it's the shipment of their products that make them successful. It's [certainly] not cheap for them to work with 4 or 5 or 6 EDA vendors - it's very expensive, which is why we push for these open standards. Having so many proprietary test structures makes it very difficult for our customers. We're hoping that this open structure will facilitate the process. Advantest is one of the main drivers on open architecture in ATE. Now that it's open, it's not a platform - which may be counterintuitive. But we don't make money by selling interfaces. That's not how we make our money. Anything we can do to proliferate open standards helps our customers. Q: Would it be to Advantest's advantage to buy LogicVision or the Test Division of one of the larger EDA vendors? Sergio: In the end, our focus is on where we can add value. That's the point of having an industry and it's why we're doing open integration. But we're not good at doing everything. We have areas where we are very good and where it makes sense for us to be doing business. The ATE vendors have always worked hard to integrate with the EDA companies. The main question is, how much effort do you put into that [integration]. The question isn't whether we're in a situation to make that work [by buying EDA vendors]. There's a gap and it's not just the ATE companies who are trying to close it - it's the way all of the semiconductor companies have been structured, not talking to each other. Q: Where will test be in 10 years? Stephen: Well, let me look into my crystal ball. Ten years from now, Big Iron will still be here, but it will be very different. You'll always see the need for power and clocking - and RF is the example today. You'll always have a need for external equipment to drive the devices for testing. It will be a different Big Iron, but nonetheless, it will still be there. Small Iron will continue to increase. And there will probably be niches [related to the complexities] - not to minimize the extent of those niches - where Small Iron will handle those complexities. Ric: There has always been somewhat of an extreme hit in terms of functional testing, both in the complexity of the programs developed to handle it and in the robustness of the production worthiness of high-performance functional testing in production. I believe we'll continue to see a trend where more and more complexity on the devices will drive things from external testing to more internal testing of the device - which will lead to more Little Iron. If you're looking at the observability of a device from the Big Iron/traditional point of view, you're looking at hundreds or thousands of points of access. But [if you look at the ability to observe the device from an internal point of view], you have millions of points of access. David: I don't disagree, but I also hope that in 10 years all of these issues will be looked at more holistically. It's very clear, even now, that in test and design, etc., the tools that customers have to deal with aren't perfect. We're looking to compensate today, but in 10 years - with advances in physics and technology - it will be absolutely paramount that we have a clear understanding of where the strengths and weaknesses are, that the yield enhancement and failure analysis tools are in the hands of the right people - those who needs those capabilities. Why doesn't Advantest buy the EDA companies in test or the test divisions of the big EDA companies? You have to look at the nuts and bolts of deployment. The EDA vendors know how to sell software, but we have no clue on how to sell hardware - and vice versa. Meanwhile, as far as test is concerned - certainly in 10 years, I hope we'll be doing a heck of a lot better than we're doing right now. Sergio: I think our goal it not to have Big or Little Iron, but to have "Flexible Iron." If we can achieve an ATE architecture, a smaller architecture, design characterization, and protection for DC-to-RF devices, and then deal with a mix of structures and functional capabilities, where you're not committed to any particular point, you can then reconfigure those points anywhere along the [test] system. Right now it costs anywhere from 100 dollars to 2,000 dollars per pin for testing. The part that's challenging is to have the structures and software to do that. The way to do that, in fact, is to have the entire industry working on it. In our designs and our structures, we see implementation underway. Different vendors are working on different versions of the architectures, but that always takes time. Right now, I think it's going to take 3-to-5 years to get it done. If you're the company with the right design tools and products to implement these structures based on a methodology - tools that allow designers to just implement [on-chip test structures] right at the end of the design process - the designer just adds a module, brings up a driver and says, "Go." But right now, designers can't predict how those complexities are going to move. [Certainly], you can't just say that you're just going to do this as an individual company. It's just impossible. This is something that has to be achieved as an industry. Q: Why not dispense with all of these issues by simply designing and producing perfect chips in the first place? Stephen: We're going to strive for that [goal], but we're definitely not there yet. Ric: The economics of test [might inspire that goal], but I'm skeptical that it's really possible. Sergio: We already can make perfect devices today, but these are pretty boring. We'll always be pushing the envelope [with new designs] such that those products are never perfect. David: And - is it a perfect device from a design process or a manufacturing perspective? I think it's pretty clear that we've all got job security for quite some time to come. (Editor's Notes : 1 - Per David Hsu, "The 'vector hospital' was where devices that failed on the tester went for failure analysis and debug. The process involved deducing a physical or logical reason from the failing ATE vectors - a grueling, tedious, and difficult process. Today, demand for diagnostics capabilities that can directly take in failing tester data and automatically deduce the logic and physical causes for this test data is rapidly growing." 2 - Thanks to all participants for their courtesy and good manners during this discussion. Some of these guys are arch competitors, but they were very polite nonetheless. 3 - Kudos to Lou Covey from VitalComPR for assembling this panel.) Industry News - Tools and IP Agilent Technologies Inc. announced the availability of the Agilent Integrated Circuit Characterization and Analysis Program (IC-CAP) 2004. The company says the IC-CAP modeling toolset helps modeling engineers, device designers, and fabrication process engineers in the RF, digital, analog and microwave technologies by enabling the development of highly accurate device models. Per the Press Release: "The plot optimizer in IC-CAP 2004 performs simultaneous optimization routines for an unlimited number of model parameters. IC-CAP 2004 incorporates the data display and optimization capabilities of Agilent's Advanced Design System (ADS), making parameter extraction, optimization and documentation procedures more efficient." CoWare Inc. and MIPS Technologies, Inc. announced that the first SystemC-based processor support package (PSP) for the MIPS64 25Kf core has been added to CoWare's ConvergenSC Model Library. The companies say that, "together with CoWare's ConvergenSC system-level design solution, the PSP helps reduce overall design time for customers of MIPS Technologies by allowing them to explore and debug their designs at the system level." Jack Browne, Vice President of Worldwide Sales at MIPS, is also quoted in the Press Release: "We are working closely with CoWare to produce SystemC-based models that provide the industry's best solution for our mutual customers' design needs. This new offering from CoWare will help OEM customers who are using the 25Kf core to focus on product design without worrying about model integration." MIPS Technologies was also busy leveraging its visibility at the Consumer Electronics Show (CES) last week in Las Vegas. MIPS announced technology developments from a number of different companies whose news from CES included MIPS-based product releases. Summarizing the MIPS Press Release: "Advanced Micro Devices announced that it would combine its MIPS-Based Alchemy Au1100 processor with the software ecosystem of Mediabolic, Inc. to create platforms for mobile entertainment products. ATI Technologies introduced the MIPS-Based XILLEON 210VC, which the company claims is the world's first digital terrestrial and Cable Plug-and-Play Television-on-Chip. Royal Philips Electronics launched what it claims is the world's first DVD+R/+RW and hard disk drive (HDD) combination semiconductor reference design. The MIPS-Based Nexperia Home complete reference design will enable DVD recorder manufacturers that do not have in-house DVD+RW/HDD chip solutions to introduce DVD+R/+RW video recorders with integrated HDD in 2004, in time for the next holiday buying season. QuickLogic Corp. announced that it partnered with OASIS SiliconSystems AG with the goal of leveraging silicon and software technology from both companies to release reference platforms optimized for a series of in-car telematics applications, including gateways and rear-seat infotainment systems. At the core of the architecture for each of these reference platforms is one of the QuickMIPS family of programmable system-on-a-chip devices and OASIS' Media Oriented Systems Transport (MOST) networking devices. ViXS Systems announced several new partners and customers that have integrated ViXS' MIPS-Based XCode II video processor and Matrix wireless chip into their next generation displays and media gateway products. The design wins include Arcadyan (Philips/Accton), Daewoo Electronics, Gemtek Technologies, Nexgen Mediatech (Chi-Mei Corp.) and Toshiba." Finally, also from MIPS - The company, in conjunction with WIS Technologies, Inc., announced that the two companies have entered into a licensing agreement where WIS Technologies will incorporate a 32-bit core from MIPS Technologies in its future product line for the digital consumer marketplace. Cadence Design Systems, Inc. announced that eInfochips has adopted the Cadence Incisive verification platform to meet its design and verification requirements, and that the company will use the Cadence platform in its ASIC design division. Samir Shroff, Director of the ASIC Design Division at eInfochips, is quoted: "As a technology company dealing with SystemC designs, it is paramount that we have a design environment where we can simulate SystemC blocks with RTL. It is imperative that simulation performance and the detailed code coverage capability are excellent. After a thorough examination of all of the products available on the market, we determined that the Cadence Incisive platform would meet all of our technical needs." Meanwhile, Cadence Design Systems, and 0-In Design Automation, Inc. announced that they have combined efforts to provide "superior verification solutions to the market." Cadence says it will integrate and license 0-In's library of assertion checkers, protocol monitors, assertion synthesis, and assertion management technology. 0-In's library of verification IP will be integrated with Cadence's Incisive platform. Ping Chao, Executive Vice President and General Manager of the Design and Verification division for Cadence, is quoted: "The integration of 0-In's leading library-based assertion approach with the Incisive platform will help designers and verification engineers verify faster, more efficiently and more thoroughly. The relationship with 0-In demonstrates our overall strategy of open collaboration with industry leaders to provide customers with the most critical solutions for their design and verification needs." Magma Design Automation Inc. announced that IBM Microelectronics is accepting design data from Blast Create for implementation of ASIC designs. Per the Press Release: "Designs validated by IBM's ASIC methodology group have shown the handoff from Blast Create to provide a high degree of correlation with IBM's static timing tool, Einstimer, a part of IBM's physical design system, Chip Bench." Maurice Kinney, Synthesis Methodology Engineer at the IBM Technology Group, is quoted in the Press Release: "This provides our customers additional synthesis tool choices for implementing ASIC designs." ReShape Inc. announced that the company's PD Optimizer chip optimization software will support the AMD Opteron and AMD Athlon 64-bit processors running Red Hat Enterprise Linux 3. Per the Press Release: "For example, on a 4.6 million instance hierarchical SoC design, ReShape's tools running on a 1.8GHz Athlon machine prepared 20 individual blocks ready for place and route in only six hours, starting from a new netlist. Over eight benchmarks, chip die size was reduced by an average of 15 percent. In addition, top-level interconnect was reduced by an average of 26 percent, and global repeaters and buffers were reduced by an average of 41 percent. These optimizations, combined, result in a lower cost die with less signal latency." That's good news for ReShape. Coming soon to a theater near you ISQED 2004 - The 5th annual International Symposium on Quality Electronic Design will be taking place from March 22nd to the 24th at the DoubleTree Hotel in San Jose, CA. Organizers say, "ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues. [The conference] includes three parallel tracks, with upwards of 100 technical presentations, six keynote speakers, three panel discussions, workshops /tutorials and other informal meetings." In other words, there will be lots to see and lots to do, so you're going to be wanting to be making arrangements to attend this one. ( www.isqed.org ) Newsmakers Carbon Design Systems announced today that it has raised a $10 million series B second round of funding in "just 90 days." (Editor's Note: A difficult metric to evaluate, however, as it's not clear how long such an effort normally takes.) Participating venture capital firms included Matrix Partners and existing series A investors Commonwealth Capital, Flagship Ventures, and Allan Wallack. Carbon says this round of investment brings the company's total financing to $15 million. Carbon Design also announced that Will Herman, former Viewlogic, Innoveda, and Silerity CEO, will join Carbon's Board of Directors along with Edgar Masri of Matrix Partners. Steve Butler, President and CEO of Carbon, is quoted in the Press Release: "We are pleased that Will Herman and Edgar Masri are joining a seasoned Board that includes Allan Wallack, former CEO of Spring Tide Networks and Chrysalis Symbolic Design." Circuit Semantics, Inc. has formally recounted several "significant milestones" in 2003 and the company's 2004 product plan. Last year, the company licensed its patents for $9 million, closed a $1.6 million funding round with previous investors VenGlobal and Crescent Ventures leading the round, and moved its headquarters to Mountain View, CA. Ewald Detjens, President and CEO of Circuit Semantics, is quoted in the Press Release: "The round of VC funding, licensing income, and growing interest from current and new customers are the elements that are allowing us to expand our staff and add new capabilities to our products this year." That is good news, formal or otherwise. Infineon Technologies announced the establishment of an IC design center and a new subsidiary - Infineon Technologies Xi'an Co., Ltd. - in Xi'an, China. The company says this "represents another move of the company's steady business expansion and long-term presence in the Chinese market. Strategically located at Xi'an High-Tech Park, the new IC Design Center plays a vital role for integrated circuit design for all of Infineon's business groups, with the primary focus on developing innovative applications for communications as well as for automotive and industrial electronics. The new IC Design Center will enable Infineon to better serve the customers' needs and to harness the R&D talents in Western China to foster greater technology innovation." InTime Software Inc. announced the availability of on-demand demonstrations of the company's Time Planner and Time Director software. The company says that demos can be viewed over the Internet by registering at the InTime Software website. Tera Systems, Inc. announced expanded global operations with the addition of a European headquarters, a new distributorship serving the south-central U.S., and increased staff in Japan. In addition, the company says it has appointed Larry Rawstorne as General Manager of Tera Systems, Europe. Alain Labat, President and CEO, is quoted: "RTL design planning is capturing increased attention as companies recognize the significant cost-advantages of visibility into back-end design issues early in the design cycle. Extending our operations globally gives Tera the opportunity to better serve our growing customer base at the local level." Bits & Bytes 1 - Playing the markets Cadence Design Systems says it has joined an initiative that will enable the company to list its stock on both the NASDAQ and the New York Stock Exchange. Cadence says it's joining 5 "market leaders" - Apache Corp., Charles Schwab, Countrywide Financial, HP, and Walgreens - in launching the initiative, announced by the Nasdaq Stock Market. According to the Press Release: "The dual listing will provide two immediate benefits: more choices for Cadence investors, and greater liquidity for the stock." Ray Bingham, President and CEO at Cadence, is also quoted: "This is an innovative program that recognizes the realities of today's trading environments, which demand more choices and greater efficiencies." I'll admit that it's a mystery to me who benefits from this move, but then I'm neither an economist, nor a "market leader." 2 - Summit Design Summit CEO Guy Moshe and I had a chance to speak by phone recently. Guy was sitting in the Summit offices in Israel, and responded to a number of different questions on a range of topics. He was clearly optimistic about the improving global economy and the growing opportunities for electronic system level (ESL) design. Guy said, "We're currently looking at what will be our next step in [the growth of the company], including another round of financing. We want to grow the company and we need to grow it fast [to meet market demand]. Currently, we're looking to build larger Sales and Marketing activities. We have about 72 employees and are planning to reach 90 employees by the end of 2004." "I think the economy is showing very positive signs - companies are spending more money and the system-level design space is gaining more and more momentum. Overall, we're seeing larger demand, so we want to be prepared for that. Up until now, we've been growing at 20 percent per quarter, [a growth rate] which has shown us that we should be increasing our business." "The bulk of our customers are in two areas - in the U.S. and in Japan. Economy wise, Europe has been struggling more than in North America. They're still on tight budgets there and very cautious [about spending]. In 2003 we didn't really grow our customer base in Europe, but we did maintain our installed base. In 2003, we decided to focus on Japan and North America. We have some new customers in North America - Northrop Grummand among them. Our new customers reflect two new markets of strength for us, storage area networking and the defense industry. [Meanwhile], Europe is made up of some very big accounts - Philips, Siemens, Alcatel, STMicroelectronics. You need a lot of resources to penetrate major accounts, and in 2004 we'll be back focusing on Europe." "I think that ESL design is mainly targeted at projects that are more sophisticated, with larger capacity and complexity. If you look in the storage area, for example, the disk space involved in dealing with those amounts of data is huge. A TiVo-type product - one that allows you to record a television program to view later - is a product that has to go through a lot of testing to verify the hardware and software together. Those products require more co-development. Those are the types of customers who are needing the solutions provided by ESL tools. Look at the problems that people are facing in verifying hardware and software together. We're offering them a methodology such that, early on in the process, the hardware and software guys can work together." "Traditional chip designers have less concerns here because they're still making large ASICs without worrying about the software. I think ASIC designers will continue to exist, but as the number of new ASIC starts is getting lower and lower - the NRE costs for ASIC prototyping more and more expensive - the number of people doing ASICs is decreasing. Meanwhile, growth in the FGPA market is increasing, the piece that involves the more sophisticated FPGAs. Xilinx has new product families, as does Altera and others, which include embedded processors inside the FPGA. We intend to actively and successfully pursue those markets, as well." "There is always going to be a partition between various vendors, but you're seeing more and more start-ups in ESL. One type of start-up is providing architectures in the verification space and the another type is in the embedded processor space. You'll see start-ups coming up with more and more specific solutions in both of these markets." "The traditional vendors will start to play into these markets - Mentor, Synopsys, and Cadence - and they'll need things in their portfolios that can only be achieved through cooperation [with start-ups], or through their own internal development. For these companies [to consider purchasing start-ups to enhance their portfolios], first the big companies need to see proof that this new ESL market will grow. They will not immediately jump out and acquire the start-ups. First, they'll try to cooperate with the ESL vendors and understand the space before they do the investment. Usually the process involves a joint marketing effort, or an OEM agreement, before a big company makes the decision to acquire a smaller company." "Companies grow when they penetrate new markets. If look back over the last 6 or 7 years, the new EDA companies that came out reached 40 million or 50 million dollars and were stuck there. Those companies were usually based on just one product line. When they reached that [plateau], they had to make the choice to purchase new technology. But they couldn't control those markets, so they hesitated - which is the reason you haven't seen any new companies reaching the size of Mentor, Synopsys, and Cadence, at least for now." "In 3 or 4 years, the ESL market will grow. In fact, expectations are that it will grow very fast. I expect to see the ESL market at 800 million to 1 billion dollars. Today, ESL is starting to break down the barriers between the EDA and embedded software worlds. [Meanwhile], ESL is dealing with new languages - the C and SystemC languages - which are more common in the software world [than in the world of design]. Going forward, we'll see closer boundaries between EDA and pure electronics, and moves to software and the mechanical design space. [Consider that] every new car coming to market is saturated with electronics - those boundaries are really falling and changing the way that the whole industry looks to the vendors and to their customers." In the category of ... Copy editing extravaganza Thanks to Lori Kate Calise, Bill Bayer, Lou Covey, and Steve Schulz - among others - for the plethora of corrections they sent in for last week's newsletter. All of the corrections have been made in the on-line version of the January 12th issue of EDA Weekly. --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are registered as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your newsletter's details, including format and frequency, or to discontinue this service, please navigate to . If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . 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